Products

Description: 74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state...

The 74LS48 feature active-high outputs for driving lamp buffers or common-cathode LEDs. They have full ripple-blanking input/output controls and a lamp test input. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.  Their circuits incorporate automatic leading and/or trailing-edge...

Description: The 7483, 74LS83, and 74HC83 are integrated circuits (ICs) that function as 4-bit binary full adders. They are designed to perform the addition of two 4-bit binary numbers, providing sum outputs for each bit and a carry-out for cascading to additional stages. Key...

Description: 74HC85 4-Bit Comparator IC (7485 IC) DIP-16 Package. 74LS85 is the four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices...

The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be...

Description: The 7493 is a 4-bit binary ripple counter IC from the 74xx series. It can count from 0 to 15 (mod-16) and is widely used in frequency dividers, digital clocks, and sequential logic circuits.

Description The 74hc138 IC is a high-speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active...

Description The 774hc147 ic in are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT147 9-input priority encoders accept data from nine active LOW inputs (A0 to...

Description 74hc151 IC is 8 - Input Multiplexer 16 Pin IC. Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three binary code at select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation....

Description: 74HC157 is a high-speed multiplexer integrated circuit consisting of four 2-inputs digital multiplexers inside the chip. It is pin-compatible with Low-power Schottky TTL. It has two control inputs namely enable and select input. Additionally, it has two groups of registers. The select input...

Description: The 74HC161 is a synchronous presettable binary counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW....

The 74HC163 is a high-speed 4-bit synchronous binary counter IC with clear and load functions. It offers fast counting, parallel load capability, and is commonly used in digital clocks, frequency dividers, and sequential logic circuits.

The 74HC164/ 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for...

The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage....

Description: 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3...